The present invention relates to an output circuit, and more particularly, to an output circuit for preventing leakage current from flowing through the output circuit when a voltage higher than the power supply level is applied to the output terminal.
FIG. 1(a) is a schematic circuit diagram showing a first example of an output circuit 50 used in an electronic device. The output circuit 50 includes a push-pull circuit having a CMOS configuration. The source of a push PMOS transistor Q51 is connected to a power supply Vdd, and the source of a pull NMOS transistor Q52 is connected to the ground GND. An internal circuit (not shown) provides the gate of the PMOS transistor Q51 (i.e., internal input terminal P51) with a first internal signal in51 and the gate of the NMOS transistor Q52 (i.e., internal input terminal P52) with a second internal signal in52. The drains of the MOS transistor Q51, Q52 are connected to each other. A node between the drains (i.e., output terminal P53 of the output circuit 50) is connected to a bus line (not shown).
During normal output operation of the output circuit 50, the output circuit 50 receives the first and second internal signals in51, in52, the logic levels of which are the same, from the internal circuit. The output circuit 50 then provides a signal, the logic level of which is inverted from the levels of the first and second internal signals in51, in52, as an output data out1 to the bus line via the output terminal P53. That is, in response to the first and second internal signals in51, in52, the output circuit 50 provides the bus line with output data signals out1 having the power supply level Vdd and the ground level GND. When the first internal signal in51 provided to the MOS transistors Q51 goes high and the second internal signal in52 provided to the transistor Q52 goes low, the MOS transistors Q51, Q52 are deactivated and the output terminal P53 is set to a high impedance (Hi-Z) state.
FIG. 2 is a schematic diagram showing a second prior art example of an output circuit 60 employed in an electronic device. The output circuit 60 includes a push-pull circuit formed by connecting NMOS transistors Q61, Q62 in series between a power supply Vdd and the ground GND. An internal circuit (not shown) provides the gate of the NMOS transistor Q61 (i.e., internal input terminal P61) with a first internal signal in61 and the gate of the NMOS transistor Q62 (i.e., internal input terminal P62) with a second internal signal in62. A node between the NMOS transistors Q61, Q62 (i.e., output terminal P63 of the output circuit 60) is connected to a bus line.
During normal output operation of the output circuit 60, the output circuit 60 receives the first and second internal signals in61, in62, the logic levels of which are inverted from each other. The output circuit 60 then provides the bus line with an output data signal out2 having the same logic level as the first internal signal in61. When the internal signals in61, in62 provided to the output circuit 60 both go low, the MOS transistors Q61, Q62 are deactivated and the output terminal P63 is set to a high impedance (Hi-Z) state.
However, data having a level higher than the power supply levels of the output circuits 50, 60 may be provided to the bus line from other devices. In such case, the application of a voltage, which level is higher than the power supply, to the corresponding output terminals P53, P63 would result in the shortcomings discussed below.
In the output circuit 50, the application of a voltage higher than the sum of the power supply Vdd voltage and a forward voltage VDF between the drain and back gate of the transistor Q51 (Vdd+VDF) to the output terminal P53 would cause a leakage current to flow through the output terminal P53, the source and back gate of the PMOS transistor Q51, and to the power supply Vdd, as shown by the broken line in FIGS. 1(a) and 1(b). This is because the circuit between the source and the back gate of the PMOS transistor Q51 is equivalent to a diode connected in a forward direction.
Further, the transistor Q51 is deactivated when a voltage higher than the sum of the gate voltage of the PMOS transistor Q51 and a threshold voltage Vthp of the transistor Q51 is applied to the output terminal P53 in a high impedance (Hi-Z) state. This would cause a leakage current to flow from the bus line and to the power supply Vdd through the output terminal P53 and the drain and source of the PMOS transistor Q51, as shown by the broken line in FIGS. 1(c) and 1(d).
In the output circuit 60, leakage current does not flow when the voltage of the data signal at the bus line is higher than the power supply Vdd voltage. This is because the circuit between the drain (output terminal P63) and the back gate of the NMOS transistor Q61 is equivalent to a diode connected in a reverse direction. However, the output circuit 60 outputs the data signal out2 having a voltage lower than the gate voltage of the transistor Q61 by the threshold voltage Vthn of the NMOS transistor Q61. Accordingly, the data signal generated by the output circuit 60 cannot perform full swing between the power supply Vdd level and the ground GND level.
When a voltage higher than the power supply Vdd level is applied to each of the output terminals P53, P63, the potential difference between the output terminals P53, P63 and the associated input terminals P51, P52, P61, P62 is increased. Thus, a gate oxidation film, which is applied to each of the MOS transistors Q51, Q52, Q61, Q62 between the source and gate (FIGS. 1(b) and 1(d)), is formed with increased thickness to resist high voltages.
However, the MOS transistors Q51, Q52, Q61, Q62 must undergo a special process to form the thick gate oxidation films. This complicates the manufacturing process and increases manufacturing cost.